As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a multi-gate field effect transistor (FET) including a fin FET (FinFET). In a FinFET, a gate electrode is adjacent to three side surfaces of a channel region with a gate dielectric layer interposed therebetween. As the size of the FinFET shrinks, the electrode contact area on the S/D shrinks, thereby increasing the contact resistance. As transistor dimensions are continually scaled down, further improvements of the FinFET are required.